1. Field of the Invention
The present invention relates to a semiconductor device having a dual stress liner, a method of manufacturing the semiconductor device and a light exposure apparatus for forming the dual stress liner. More particularly, the present invention relates to a semiconductor device having a dual stress liner for increasing electron mobility, a method of manufacturing the semiconductor device, and a light exposure apparatus for forming the dual stress liner.
2. Description of the Related Art
A semiconductor device including a PMOSFET (p-channel metal oxide semiconductor field effect transistor) and an NMOSFET (n-channel metal oxide semiconductor field effect transistor) may be manufactured by repeatedly performing unit manufacturing processes, such as a film formation, an etching, an ion implantation, or the like, on a semiconductor substrate such as a silicon wafer.
Electron mobility may be decreased by the compressive stress applied to the semiconductor substrate while repeatedly performing the unit manufacturing processes. In detail, the compressive stress occurs in channel regions of the MOSFETs due to the difference of thermal expansion coefficients of materials constituting the semiconductor device and the actual or genuine stress existing in the materials. Thus, the electron mobility and saturation drain current (Idsat) are decreased in the NMOSFET, which uses electrons as its carrier.
Meanwhile, according to U.S. patent application Publication Ser. No. 2003/0040158, in a semiconductor device including an n-channel MOSFET and a p-channel MOSFET, a first silicon nitride layer having tensile stress is formed on the n-channel MOSFET, and a second silicon nitride layer having compressive stress is formed on the p-channel MOSFET. Thus, electron mobility and saturation drain current of the n-channel MOSFET are increased, and bending or warping of a substrate is reduced.
FIGS. 1 to 5 are cross-sectional views illustrating a conventional method of manufacturing a semiconductor device.
Referring to FIG. 1, a PMOSFET 20a and an NMOSFET 20b are formed on active regions defined by an isolation layer 12 formed in a surface portion of a single crystal silicon substrate 10. The PMOSFET 20a includes a gate insulating layer 22a, a gate electrode 24a, spacers 26a and impurity diffusion regions 28a which serve as source/drain regions of the PMOSFET 20a. The NMOSFET 20b includes a gate insulating layer 22b, a gate electrode 24b, spacers 26b and impurity diffusion regions 28b which serve as source/drain regions of the NMOSFET 20b. Metal silicide layers 30a and 30b are formed in top portions of the gate electrodes 24a and 24b and surface portions of the impurity diffusion regions 28a and 28b. 
Referring to FIG. 2, a first silicon nitride layer 40 having compressive stress is formed on the PMOSFET 20a and the NMOSFET 20b using a plasma enhanced chemical vapor deposition (PECVD) process, and then a first photoresist pattern 42 is formed on the first silicon nitride layer 40. The first photoresist pattern 42 exposes a portion of the first silicon nitride layer 40 on the NMOSFET 20b. 
Referring to FIG. 3, the NMOSFET 20b is exposed by selectively removing the first silicon nitride layer 40 using the first photoresist pattern 42 as an etching mask. Then, a second silicon nitride layer 44 having tensile stress is formed on the NMOSFET 20b and the first silicon nitride layer 40 using a low pressure chemical vapor deposition (LPCVD) process after removing the first photoresist pattern 42 from the substrate 10.
Referring to FIG. 4, a second photoresist pattern 46 is formed on the second silicon nitride layer 44. The second photoresist pattern 46 is formed to selectively expose a portion of the second silicon nitride layer 44 on the PMOSFET 20a. 
Referring to FIG. 5, the first silicon nitride layer 40 is exposed by selectively removing the second silicon nitride layer 44 using the second photoresist pattern 46 as an etching mask. Then, the second photoresist pattern 46 is removed from the substrate 10.
The silicon nitride layers 40 and 44 formed through the above-described processing steps may increase electron mobility of the NMOSFET 20b and improve stability of the semiconductor substrate 10. However, the conventional method has some drawbacks. Particularly, the processing steps for forming the silicon nitride layers 40 and 44 are complicated, and thus a long time for forming the silicon nitride layers 40 and 44 is required. Accordingly, the fabricating time of the semiconductor is increased, and thus the productivity of the semiconductor is deteriorated.